During the formation of a semiconductor device, many features such as word lines, digit lines, contacts, and other features are commonly formed over a semiconductor wafer. A goal of semiconductor device engineers is to form as many of these features in a given area as possible to increase yields, decrease manufacturing costs, and to miniaturize devices. The formation of these structures on a semiconductor wafer typically requires the use of lithography. Optical lithography, the lithographic method most used in leading-edge wafer processing, comprises projecting coherent light of a given wavelength, typically 248 nanometers (nm) or 193 nm, from an illumination source (illuminator) through a quartz photomask or reticle having a chrome pattern representative of features to be formed, and imaging that pattern onto a wafer coated with photoresist. The light chemically alters the photoresist and enables the exposed photoresist (if positive resist is used) or the unexposed photoresist (if negative resist is used) to be rinsed away using a developer.
With decreasing feature sizes, the limits of optical lithography are continually being tested. Improvements in feature density are made through process advances, enhanced lithographic methods referred to as resolution enhancement techniques, and improved equipment and materials.
One such process advance, depicted in FIGS. 1-6, uses a mask having repeating features of a given pitch (i.e. a given distance from the beginning of one repeating feature to the beginning of the next feature) along with the formation of various layers and selective etches to double the density of the features formed from the lithography mask. FIG. 1 depicts a semiconductor wafer substrate assembly 10 comprising a semiconductor wafer, a layer to be etched 12, for example a silicon nitride layer, a support layer 14, for example formed from carbon using chemical vapor deposition (CVD) or a spin-on technique, and a patterned masking layer 16, such as a photoresist layer formed using an optical lithographic process or a hard mask layer formed using optical lithography and an etch process. The patterned masking layer 16 may be formed at the feature size limits allowed by the lithographic process, and comprises three individual features (three periods/pitches) formed over a given distance 18.
After forming the structure of FIG. 1, an etch of the support layer 14 is performed using mask 16 as a pattern. This etch is typically an anisotropic dry etch which etches the support layer 14 selective to the layer to be etched 12 (i.e. which removes the support layer 14 with little or no etching of the layer to be etched 12). After etching the support layer 14, the patterned masking layer 16 is removed and a conformal hard mask layer 20, for example silicon dioxide, is formed to result in the structure of FIG. 2.
Subsequently, a spacer etch of the FIG. 2 structure is performed to result in the structure of FIG. 3 having spacers 20′ from the hard mask layer along sidewalls of the support layer 14. Subsequently, the support layer 14 is etched to result in the structure of FIG. 4.
Next, spacers 20′ formed from the hard mask layer are used as a pattern to etch the layer to be etched 12, which results in the structure of FIG. 5. Finally, spacers 20′ are etched selective to the layer to be etched 12 to result in the structure of FIG. 6.
The process of FIGS. 1-6 has the advantage of using optical lithography to form the masking layer 16 having three features in a given distance 18, while the completed structure depicted in FIG. 6 has six features 12 (six periods/pitches) in the original distance 18. Thus the number of features within the distance is approximately doubled without requiring an additional lithography mask.
Various techniques to increase feature density are described in U.S. Pat. No. 5,328,810 by Tyler A. Lowrey, et al. and U.S. Pat. No. 5,254,218 by Ceredig Roberts et al., both of which are assigned to Micron Technology, Inc. and incorporated herein as if set forth in their entirety.
A method for forming a semiconductor device using an optical lithography mask with a first pitch and resulting in features having a second pitch equal to 1/n, where n is an integer greater than 1 and without limitation of feature size reduction or spacing to one-half of that attainable using lithography, would be desirable.
It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which may be determined by one of skill in the art by examination of the information herein.